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| PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT PD9611 FOUR-CHANNEL PCM CODEC The PD9611 incorporates 4-channel A-law/-law PCM CODECs compliant with ITU-T Recommendation G.711/ G.714 and is suitable for applications such as PBX analog subscriber line circuits. Its gain setting circuit allows transmit/receive gain to be set for 4 channels independently by externally inputting digital signals. FEATURES * * * * * * * * * * Single-chip CMOS monolithic LSI ITU-T Recommendation G.711/G.714 compliant Four-channel PCM CODECs integrated on a single chip Compatible with A-law and -law Digital gain setting for each channel * Transmit : +7.5 to -8.0 dB (0.5 dB step) * Receive : 0 to -15.5 dB (0.5 dB step) Data transfer system: Transmit/receive synchronization Data rate: 2048 kHz +5 V single power supply Power down function for each channel Low power consumption ORDERING INFORMATION Part Number Package 48-pin shrink SOP (375 mil) PD9611GT The information in this document is subject to change without notice. Document No. S11018EJ2V0DS00 (2nd edition) Date Published October 1996 P Printed in Japan (c) 1996 PD9611 PIN CONFIGURATION (Top View) 48-pin shrink SOP (375 mil) AIN1 AOUT1 NC AIN2 AOUT2 NC ACOMIN1 ACOMOUT1 ACOMIN2 ACOMOUT2 AVDD1 AVDD2 AVDD3 AVDD4 DVDD NC PD1 PD2 PD3 PD4 FSC DCLK DX DR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 AIN4 AOUT4 NC AIN3 AOUT3 NC ACOMIN3 ACOMOUT3 ACOMIN4 ACOMOUT4 AGND1 AGND2 AGND3 AGND4 SUBGND DGND NC NC NC RST LAW SPDATA SPSYNC SPCLK ACOMIN1-ACOMIN4 AGND1-AGND4 AIN1-AIN4 AOUT1-AOUT4 AVDD1-AVDD4 DCLK DGND DR DVDD : Analog common voltage in : Analog ground : Analog signal in : Analog signal out : Analog power supply : Data clock in : Digital ground : Receive PCM data in : Digital power supply ACOMOUT1-ACOMOUT4 : Analog common voltage out PD9611GT DX FSC LAW NC RST : Transmit PCM data out : Frame synchronous clock in : A-law/-law control in : No connection : Reset in : Serial port data clock in : Serial port data in : Serial port synchronous clock in PD1-PD4 : Power down control SPCLK SPDATA SPSYNC SUBGND : Sub ground 2 PD9611 BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD4 DVDD CH1 AIN1 AOUT1 A/D D/A APD1 AIN2 AOUT2 ACOMIN1 CH2 DSP Channel FiIter APD2 ACOMIN2 AIN3 AOUT3 CH3 DX APD3 ACOMIN3 DR RST AIN4 AOUT4 CH4 I/O Linear A, DGS MUX, DEMUX APD1 APD2 APD3 SPSYNC SPCLK SPDATA LAW PD1 PD2 PD3 PD4 APD4 ACOMIN4 ACOMIN1 ACOMOUT1 ACOMIN2 ACOMOUT2 ACOMIN3 ACOMOUT3 ACOMIN4 ACOMOUT4 Voltage Reference APD4 Clock Generator FSC DCLK AGND1 AGND2 AGND3 AGND4 DGND SUBGND 3 PD9611 1. PIN DESCRIPTION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Symbol AIN1 AOUT1 NC AIN2 AOUT2 NC ACOMIN1 ACOMOUT1 ACOMIN2 ACOMOUT2 AVDD1 AVDD2 AVDD3 AVDD4 DVDD NC PD1 I/O I O - I O - I O I O - - - - - - I Name and Function Transmit analog input pin for channel 1 When not used, connect to ACOMOUT1 pin. Receive analog output pin for channel 1 Leave this pin open. Receive analog input pin for channel 2 When not used, connect to ACOMOUT1 pin. Transmit analog output pin for channel 2 Leave this pin open. Signal reference voltage input for channel 1 Signal reference voltage output for channel 1 Signal reference voltage input for channel 2 Signal reference voltage output for channel 2 Analog power supply pin for channel 1 Analog power supply pin for channel 2 Analog power supply pin for channel 3 Analog power supply pin for channel 4 Digital power supply pin Leave this pin open. Power-down control input pin for channel 1 Channel 1 enters power-down mode when this signal is low level. The output of DX pin for channel 1 becomes high-impedance and AOUT1 becomes signal reference voltage in the power-down mode. Power-down control input pin for channel 2 Channel 2 enters power-down mode when this signal is low level. The output of DX pin for channel 2 becomes high-impedance and AOUT2 becomes signal reference voltage in the power-down mode. Power-down control input pin for channel 3 Channel 3 enters power-down mode when this signal is low level. The output of DX pin for channel 3 becomes high-impedance and AOUT3 becomes signal reference voltage in the power-down mode. Power-down control input pin for channel 4 Channel 4 enters power-down mode when this signal is low level. The output of DX pin for channel 4 becomes high-impedance and AOUT4 becomes signal reference voltage in the power-down mode. Frame synchronous clock input pin (8 kHz) Data clock input pin (2048 kHz) Transmit PCM data output pin This pin outputs PCM data for channel 1 to 4 in synchronization with rising edges of DCLK after rising edges of FSC. It becomes high-impedance for other timings. Receive PCM data input pin This pin inputs PCM data for channel 1 to 4 in synchronization with falling edges of DCLK after rising edges of FSC. Setting data clock input pin Setting synchronous clock input pin Setting data input pin +5 0.25 V +5 0.25 V +5 0.25 V +5 0.25 V +5 0.25 V 18 PD2 I 19 PD3 I 20 PD4 I 21 22 23 FSC DCLK DX I I O 24 DR I 25 26 27 SPCLK SPSYNC SPDATA I I I 4 PD9611 Pin No. 28 29 Symbol LAW RST I/O I - Name and Function A-law/-law select pin in common to four channels L: A-law, H: -law Reset input, power-on reset pin H: normal operation L : internal registers are in the default status. Leave this pin open. Digital ground pin Substrate ground pin Analog ground pin for channel 4 Analog ground pin for channel 3 Analog ground pin for channel 2 Analog ground pin for channel 1 Signal reference voltage output for channel 4 Signal reference voltage input for channel 4 Signal reference voltage output for channel 3 Signal reference voltage input for channel 3 Leave this pin open. Receive analog output pin for channel 3 Transmit analog input pin for channel 3 When not used, connect to ACOMOUT1 pin. Leave this pin open. Receive analog output pin for channel 4 Transmit analog input pin for channel 4 When not used, connect to ACOMOUT1 pin. 30-32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NC DGND SUBGND AGND4 AGND3 AGND2 AGND1 ACOMOUT4 ACOMIN4 ACOMOUT3 ACOMIN3 NC AOUT3 AIN3 NC AOUT4 AIN4 - - - - - - - O I O I - O I - O I 5 PD9611 2. CAUTIONS ON USE (1) Absolute maximum ratings Application of voltage or current in excess of the absolute maximum ratings to the PD9611 may result in damage due to latch up, etc. Be especially cautions about power supply noise, etc. (2) Wiring pattern The design of the ground pattern is extremely important for operating the PD9611 with high precision. Connect the analog ground pins (AGND1 to AGND4), digital ground pin (DGND) and substrate ground pin (SUBGND) close to the IC pins, and connect to a wide analog ground line on the board. (3) Addition of bypass capacitors for power supply pins Because the PD9611 uses many internal high-frequency operational amplifiers, high power supply impedance can cause instability (such as oscillation) in these internal operational amplifiers. To suppress such instability and eliminate power supply noise, connect all power supply pins (AVDD1 to AVDD4, DVDD) close to the IC pins, and put bypass capacitors (CVDD = approximately 0.1 F) having superior high-frequency characteristics very close to the pins. (4) Addition of bypass capacitors for ACOM pins The PD9611 incorporates references voltages for signal sources. Superposing of noise on these reference voltages may have adverse effects on transmission characteristics, etc. Therefore, connect the ACOMOUT pin and ACOMIN pin close to the IC pins, and put bypass capacitors (CACOM = approximately 0.1 F) having superior high-frequency characteristics very close to the pins. (5) Control or SPDATA pin on reset When inputting the setting data from the SPDATA pin after the PD9611 is reset, first input the following patterns to reset to 0 the couter used to fetch data from the SPDATA pin. 1 clocks or more 16 clocks or more RST SPCLK SPSYNC SPDATA After ther RST pin has been set to the high level, input 1 clock or more to the SPCLK pin, set the SPSYNC pin to the high level and input 16 clocks more to the SPCLK pin. During this operation, the SPDATA pin is held at the low level. Afterwards, input the setting data. 6 PD9611 3. GENERAL OPERATION (1) PCM data transfer In the transmit section, if FSC pin is set to the high level in synchronization with the rising edge () of the data clock applied to the DCLK pin, the DX pin becomes active and sign bit data (MSB) of channel 1 is output. The following data of 7 bits is clocked out in synchronization with the rising edge () of each data clock. Sign bit data (MSB) of channel 2 is output in synchronization with the rising edge () of the 9th data clock. In the same manner, each data up to channel 4 is output and the rising edge () of the 33rd data clock then sets the DX pin to high-impedance state. Similarly, in the receive section, if the FSC pin is set to the high level in synchronization with the rising edge () of the data clock applied to the DCLK pin, data of DR pin is latched by the falling edges () of the data clock and consecutively clocked in. (2) Power down control The PD9611 has the following two methods for power down control and is able to control power-down independently for each channel. * Sets pins PD1 to PD4 to high or low level. * Inputs 8-bit setting data from SPDATA pin (see (5) Control of SPDATA pin). Internal data is the logical sum of PD1 to PD4 pin state and 8-bit setting data input. If the internal data is 0, the channel enters the power-down state. If the internal data is 1, the channel enters the power-up state. In the power down state, PCM data in the channel goes to high-impedance state and analog output becomes the signal reference voltage level. 8-Bit Setting Data (Channel 1) 0 1 0 1 PD1 Pin 0 0 1 1 Internal Data 0 1 1 1 Remarks 1. 0: Power down, 1: Power up 2. The settings are the same for channel 2 to channel 4. 7 PD9611 (3) A-law/-law control The PD9611 has the following two methods for A-law/-law control. * Sets LAW pin to high or low level. * Inputs 8-bit setting data from SPDATA pin (see (5) Control of SPDATA pin). Internal data is the logical sum of LAW pin state and 8-bit setting data input. If the internal data is 0, the PD9611 enters A-law mode. If the internal data is 1, the PD9611 enters -law mode. 8-Bit Setting Data 0 1 0 1 LAW Pin 0 0 1 1 Internal Data 0 1 1 1 Remark 0: A-law, 1: -law (4) Gain Setting control for transmit/receive The PD9611 can control gain settings independently for the transmit/receive by inputting 8-bit setting data (see (5) Control of SPDATA pin) from the SPDATA pin for four channels. Gain can be set from +7.5 to -8.0 dB for the transmit and +0.0 dB t o -15.5 dB for the receive in 0.5 dB steps. 8-bit setting data input from SPDATA pin specifies the channel set in the first 8 bits, and performs selection of transmit/receive and gain setting in the second 8 bits. 8 PD9611 (5) Control of SPDATA pin If SPSYNC pin is set to the high level in synchronization with the rising edge () of the data clock applied to the SPCLK pin, data of the SPDATA pin is latched by the falling edge () of the data clock and consecutively fetched in. After the 8-bit data has been fetched, the setting operation is performed according to the data. This setting operation is performed during the 8 clocks after fetching the data and the next data is valid at the 17th clock. Therefore, when setting 1 word (8 bits) of data, input 17 clocks or more to the SPCLK pin. SPSYNC SPCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SPDATA Don't care Data fetch Setting operation Setting completed (The next data is valid.) Ensure that 17 clocks or more are input to the SPCLK pin between the rising of SPSYNC and the rising of the next SPSYNC. SPSYNC SPCLK 17 clocks or more 9 PD9611 * A/-law, power down control D7 1 D6 0 D5 - D4 A/ D3 PD1 D2 PD2 D1 PD3 D0 PD4 0/1 Power down/power up for channel 4 0/1 Power down/power up for channel 3 0/1 Power down/power up for channel 2 Note 1 Note 1 Note 1 0/1 Power down/power up for channel 1Note 1 0/1 Setting of A-law/ -lawNote 2 - 0 1 Don't care Identification code Identification code Notes 1. 2. Default setting is power down mode. Default setting is A-law mode. * Transmit/receive gain setting control (1st word) D7 0 D6 1 D5 - D4 - D3 ch1 D2 ch2 D1 ch3 D0 ch4 0/1 Gain non-setting/setting for channel 4 0/1 Gain non-setting/setting for channel 3 0/1 Gain non-setting/setting for channel 2 0/1 Gain non-setting/setting for channel 1 - - 1 0 Don't care Don't care Identification code Identification code Transmit/receive gain setting control (2nd word) D7 1 D6 1 D5 X/R D4 D3 D2 D1 D0 Setting data 0/1 Gain setting 0/1 Gain setting 0/1 Gain setting 0/1 Gain setting 0/1 Gain setting 0/1 Transmit/receive setting 1 1 Identification code Identification code 10 PD9611 Table of Gain Setting Codes (1/2) Setting Item Setting Level Gain setting for transmit +7.5 dB +7.0 dB +6.5 dB +6.0 dB +5.5 dB +5.0 dB +4.5 dB +4.0 dB +3.5 dB +3.0 dB +2.5 dB +2.0 dB +1.5 dB +1.0 dB +0.5 dB 0.0 dB Note -0.5 dB -1.0 dB -1.5 dB -2.0 dB -2.5 dB -3.0 dB -3.5 dB -4.0 dB -4.5 dB -5.0 dB -5.5 dB -6.0 dB -6.5 dB -7.0 dB -7.5 dB -8.0 dB 1st Word 2nd Word D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 - - ch1 ch2 ch3 ch4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note Default setting 11 PD9611 (2/2) Setting Item Setting Level Gain setting for receive 0.0 dB Note -0.5 dB -1.0 dB -1.5 dB -2.0 dB -2.5 dB -3.0 dB -3.5 dB -4.0 dB -4.5 dB -5.0 dB -5.5 dB -6.0 dB -6.5 dB -7.0 dB -7.5 dB -8.0 dB -8.5 dB -9.0 dB -9.5 dB -10.0 dB -10.5 dB -11.0 dB -11.5 dB -12.0 dB -12.5 dB -13.0 dB -13.5 dB -14.0 dB -14.5 dB -15.0 dB -15.5 dB 1st Word 2nd Word D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 - - ch1 ch2 ch3 ch4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Note Default setting 12 PD9611 Gain setting control is set by inputting 8-bit data fo the 1st word first and inputting 8-bit data of the 2nd word in synchronization with the next rising edge of SPSYNC. However, if data other than the identification code of the 2nd word is input after the input of the 1st word, the contents of the 1st word are ignored. (i) When gain setting control is valid SPCLK SPSYNC SPDATA 10001111 A/ -law, power down control (valid) 01001111 Gain setting control (1st word) (valid) 11011111 Gain setting control (2nd word) (valid) (ii) When gain setting control is invalid -1 SPCLK SPSYNC SPDATA 01001111 Gain setting control (1st word) (invalid) 10001111 A/ -law, power down control (valid) 11011111 Gain setting control (2nd word) (invalid) Remark Because A/-law, power down control is input after input of gain setting control (1st word), gain setting control (1st word) becomes invalid and gain setting control (2nd word) also becomes invalid. (iii) When gain setting control is invalid -2 SPCLK SPSYNC SPDATA 11011111 Gain setting control (2nd word) (invalid) 01001111 Gain setting control (1st word) (invalid) 10001111 A/ -law, power down control (valid) Remark Because gain setting control (2nd word) is input before gain setting control (1st word), gain setting control (1st word) becomes invalid. Then, because A/-law, power down control is input even if gain setting control (1st word) is input, gain setting control (1st word) becomes invalid. 13 PD9611 4. ELECTRICAL SPECIFICATIONS (PRELIMINARY) ABSOLUTE MAXIMUM RATINGS (TA = 25 C) Item Supply voltage Analog input voltage Digital input voltage Voltage applied to analog output pin Voltage applied to digital output pin Power dissipation Ambient operating temperature Storage temperature Symbol VDD VAIN VDIN VAOUT VDOUT PT TA Tstg Condition AVDD1, AVDD2, AVDD3, AVDD4, DVDD AIN1, AIN2, AIN3, AIN4, ACOMIN1, ACOMIN2, ACOMIN3, ACOMIN4 DR, DCLR, FSC, LAW, PD1, PD2, PD3, PD4, SPCLK, SPSYNC, SPDATA, RST AOUT1, AOUT2, AOUT3, AOUT4, ACOMOUT1, ACOMOUT2, ACOMOUT3, ACOMOUT4 DX Rating -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to VDD +0.3 500 -20 to +85 -65 to +150 mW C Unit V Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATION CONDITIONS (TA = -20 to +85 C, VDD = 5 V 5 %, GND = 0 V, fDCLK = 2048 kHz) (1) DC condition Item Ambient operating temperature Supply voltage Analog input voltage Analog output load resistance Analog output load capacitance High level input voltage Symbol TA VDD VAI RLOAD CLOAD VIH1 VIH2 Low level input voltage VIL1 VIL2 DR, DCLK, FSC, LAW, PD1, PD2, PD3, PD4, SPCLK, SPSYNC, SPDATA RST DR, DCLK, FSC, LAW, PD1, PD2, PD3, PD4, SPCLK, SPSYNC, SPDATA RST 2.0 0.8xVDD 0 0 AVDD1, AVDD2, AVDD3, AVDD4, DVDD Condition MIN. -20 4.75 TYP. +25 5.0 MAX. +85 5.25 +1.0 k 50 VDD VDD 0.8 0.2xVDD pF V Unit C V AIN1, AIN2, AIN3, AIN4 (ACOM as reference) -1.0 AOUT1, AOUT2, AOUT3, AOUT4 50 14 PD9611 (2) AC condition Item Data clock frequency Data clock pulse width Frame synchronous clock frequency High level frame synchronous pulse width Low level frame synchronous pulse width Clock rise time Clock fall time Float in synchronous timing Symbol fCLK tCLK fs tWHS tWLS tR tF tCSD1 tCSD2 Frame synchronous clock and data clock high level width DR setup time DR hold time SPDATA clock frequency SPDATA setup time SPDATA hold time Float in SP synchronous timing tWHSC tDSR tDHR fSPCLK tGSR tGHR tFSD Note Note 100 100 40 Note Note 40 100 65 120 2048 50 ppm 200 8 50 50 100 Condition (= 1/tCY) 50 ppm 200 8.0 MIN. TYP. 2048 MAX. Unit kHz ns kHz ns s ns ns ns ns ns ns ns kHz ns ns ns Note Set the rise time and fall time of the digital input waveform and clock signal used for measuring timings to 5 ns. 15 PD9611 DC CHARACTERISTICS (TA = -20 to +85 C, VDD = 5 0.25 V, GND = 0 V, fDCLK = 2048 kHz, and all output pins are unloaded.) (1) Power consumption Item Circuit current Power-down circuit current Symbol IDD IDDPD Condition All channels in normal operation All channels in power-down mode MIN. TYP. 23 5 MAX. 30 6 Unit mA (2) Digital interface Item Digital input current Symbol IID Condition DR, DCLK, FSC, LAW, PD1, PD2, PD3, PD4, SPCLK, SPSYNC, SPDATA, RST Each pin 0 VDIN VDD DX pin DX pin DX pin 0 VDIN VDD IOH = -150 A IOL = 0.8 mA MIN. -10 TYP. MAX. +10 Unit A 3-state leakage current High level output voltage Low level output voltage Digital output pin output capacitance Digital input pin input capacitance IL VOH VOL COD CID -10 VDD-0.3 +10 V 0.4 15 10 pF f = 1 MHz, 0 V other than unmeasured pins f = 1 MHz, 0 V other than unmeasured pins (3) Transmit amplifier (AIN1, AIN2, AIN3, AIN4 pins) Item Input bias current Input resistance Input capacitance Symbol IB RIN CIN Condition MIN. -10 1 10 TYP. MAX. +10 Unit A M pF (4) Receive power amplifier (AOUT1, AOUT2, AOUT3, AOUT4 pins) Item Output offset voltage Maximum output voltage Output resistance Symbol VOA VOM ROUT Condition DR = +0 code ACOM as reference ACOM as reference MIN. -50 -1.02 1 TYP. MAX. +50 +1.02 Unit mV V (5) Signal reference voltage output (ACOMOUT1, ACOMOUT2, ACOMOUT3, ACOMOUT4 pins) Item Output voltage Symbol VACOM Condition MIN. 2.35 TYP. 2.4 MAX. 2.45 Unit V 16 PD9611 AC CHARACTERISTICS (TA = -20 to +85 C, VDD = 5 0.25 V, GND = 0 V, fDCLK = 2048 kHz) Item Data enable delay time Symbol tDZX1 tDZX2 Data delay time Data hold time tDDX tHZX Condition DX when FSC is behind DCLK DX when FSC is ahead of DCLK DX pin DX pin 25 MIN. TYP. MAX. 100 100 100 Unit ns ns ns ns 17 PD9611 TIMING CHARTS (1) Transmit timing (a) When FSC is ahead of DCLK tR tWHS tF tWLS FSC tWHSC tCSD2 tCY tR tCLK tF DCLK 1 2 8 tCLK tDZX2 Hi-Z tDDX tHZX Hi-Z DX MSB 2nd 7th LSB (b) When FSC is behind DCLK FSC tCSD1 tWHSC DCLK 1 2 8 tDZX1 Hi-Z Hi-Z DX MSB 2nd 7th LSB 18 PD9611 (2) Receive timing (a) When FSC is ahead of DCLK tR tWHS tF tWLS FSC tWHSC tCSD2 tCY tR tCLK tF DCLK 1 2 8 9 tDSR tCLK tDHR tR, tF tR, tF DR Don't care MSB Don't care 2nd 7th Don't care 8th (b) When FSC is behind DCLK FSC tCSD1 tWHSC DCLK 19 PD9611 (3) Gain setting timing SPSYNC tFSD SPCLK 1 tGSR tGHR 2 3 8 9 SPDATA Don't care D7 Don't care D6 Don't care D5 Don't care D1 Don't care D0 Don't care Remark The relationship between SPSYNC and SPCLK is the same as in the receive timing. DX output measuring circuit Timing test waveform All inputs/outputs other than DX pin 2.0 V Test points 2.0 V 0.8 V VDD 2 k DX 165 pF Output 0.8 V DX pin output 2.4 V 0.4 V Test points 2.4 V 0.4 V (4) Transmit, receive PCM data input/output timing charts 1 DCLK (2.048 MHz) 2 3 4 5 6 7 8 9 10 11 12 13 28 29 30 31 32 33 256 1 2 3 4 FSC (8.0 kHz) Channel 1 data DX Hi-Z Channel 2 data Channel 4 data D4 D3 D2 D1 D0 LSB Channel 4 data D4 D3 D2 D1 D0 LSB Don't care Hi-Z Channel 1 data D7 D6 D5 D4 SB Channel 1 data D7 D6 D5 D4 MSB D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 MSB Channel 1 data LSB MSB Channel 2 data DR Don't care D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 MSB LSB MSB 20 PD9611 (5) Setting data input timing 1 SPCLK 2 3 4 56 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 SPSYNC Setting data Don't care SPDATA D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB Don't care Setting data D7 D6 D5 D4 MSB 21 PD9611 TRANSMISSION CHARACTERISTICS (TA = -20 to +85 C, VDD = 5 0.25 V, GND = 0 V, fDCLK = 2048 kHz) Item Zero transmission level point (transmit) Zero transmission level point (receive) Symbol OTLPX OTLPX Condition Referenced to 600 Referenced to 600 Setting Value -3.8 -3.8 Unit dBm dBm Item Insertion loss Symbol IL A/D input signal 0 dBm0 1 kHz D/A input signal 0 dBm0 1 kHz Condition MIN. -0.3 -0.3 60 Hz 200 Hz 300 to 3000 Hz 3200 Hz 3400 Hz 3780 Hz 24.0 0 -0.15 -0.15 0 +6.5 -0.15 -0.15 0 +6.5 -0.2 -0.5 -1.0 -0.2 -0.5 -1.0 36 30 25 36 30 25 TYP. MAX. +0.3 +0.3 - 2.0 +0.15 +0.65 0.8 Unit dB Transmission loss frequency characteristics FRX A/D Reference input signal 1015 Hz 0 dBm0 dB FRR D/A Reference input signal 1015 Hz 0 dBm0 0 to 3000 Hz 3200 Hz 3400 Hz 3780 Hz +0.15 +0.65 +0.8 Gain tracking (tone method) GTX A/D Reference input signal -10 dBm0 f = 700 to 1100 Hz +3 to -40 dBm0 -50 dBm0 -55 dBm0 +3 to -40 dBm0 -50 dBm0 -55 dBm0 +3 to -30 dBm0 -40 dBm0 -45 dBm0 +3 to -30 dBm0 -40 dBm0 -45 dBm0 +0.2 +0.5 +1.0 +0.2 +0.5 +1.0 dB GTR D/A Reference input signal -10 dBm0 f = 700 to 1100 Hz Transmit/receive channel overall power distortion ratio (tone method) SDX A/D Input signal f = 700 to 1100 Hz dB SDR D/A Input signal f = 700 to 1100 Hz Absolute delay characteristic Absolute delay distortion frequency characteristics DA DO A/A Input signal = 0 dBm0 A/A 500 Hz 600 Hz 1000 to 2600 Hz 2800 Hz 540 1400 700 200 1400 -72 -80 18 10 s s Idle channel noise ICNADA ICNDAA ICNAD ICNDA A/D A-law Psophometric weighted D/A A-law Psophometric weighted A/D -law C-message weighted D/A -law C-message weighted dBm0p dBrnc0 22 PD9611 Item Cross talk between channels Power supply rejection ratio Coder offset Mutual modulation (2 tones) IMD Symbol CT PSRR Condition A/A Input signal = 0 dBm0 AVDD1, AVDD2, AVDD3, AVDD4, DVDD = 5 V 100 mVP-P A/D Input signal 0 V A/D Input signal: f1, f2; 300 to 3400 Hz, -4 to -21 dBm0 Measuring signal: 2 x f1 - f2 level (2 x f1 - f2) vs level (f1, f2) D/A Input signal: f1, f2; 300 to 3400Hz, -4 to -21 dBm0 Measuring signal: 2 x f1 - f2 level (2 x f1 - f2) vs level (f1, f2) Discrimination A/D Input signal: f; 4396 to 7796 Hz 0 dBm0 Measuring signal: 8000 - fHz D/A Input signal: f; 204 to 3604 Hz 0 dBm0 Measuring signal: 8000 - fHz A/D Input signal: f; 700 to 1100 Hz 0 dBm0 Measuring signal: Any frequency D/A Input signal: f; 700 to 1100 Hz 0 dBm0 Measuring signal: Any frequency Single frequency noise NSF D/A Gain setting = 0 dB Measuring signal: f = up to 256 kHz A/D difference from reference setting value D/A difference from reference setting value -0.15 -0.15 -5 44.0 MIN. TYP. MAX. -70 -25 +5 Unit dB dB - dB 44.0 dB -27 dB Out-of-band spurious -27 dB In-band spurious -45 dB -45 dB -54 dBm0 Transmit gain setting Receive gain setting DGSX DGSR +0.15 +0.15 dB 23 PD9611 5. APPLICATION CIRCUIT EXAMPLE VDD 0.1 F AVDD1 AVDD2 AVDD3 AVDD4 DVDD 0.1 F AIN1 AOUT1 CH1 A/D D/A DSP Channel FiIter 100 k ACOMIN1 APD1 100 k 0.1 F AIN2 AOUT2 ACOMOUT1 APD2 AIN3 AOUT3 ACOMOUT1 APD3 AIN4 AOUT4 ACOMOUT1 APD4 ACOMIN4 APD1 APD2 APD3 APD4 ACOMIN3 CH4 ACOMIN2 CH3 ACOMIN1 CH2 VDD 2 k DX DR RST SPSYNC I/O Linear A, DGS MUX, DEMUX SPCLK SPDATA LAW PD1 PD2 PD3 PD4 DX DR RST SPDATA LAW PD1 PD2 PD3 PD4 SPCLK SPSYNC ACOMIN1 ACOMOUT1 0.1 F 0.1 F 0.1 F 0.1 F AGND1 AGND2 ACOMIN2 ACOMOUT2 ACOMIN3 ACOMOUT3 ACOMIN4 ACOMOUT4 Voltage Reference FSC Clock Generator DCLK DCLK FSC AGND3 AGND4 DGND SUBGND 24 PD9611 6. PACKAGE DRAWINGS 48 PIN PLASTIC SHRINK SOP (375 mil) 48 25 detail of lead end 1 A 24 H G 3+7 -3 I J F C D MM N B E K L P48GT-65-375B-1 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N MILLIMETERS 16.21 MAX. 0.63 MAX. 0.65 (T.P.) 0.30 0.10 0.125 0.075 2.0 MAX. 1.7 0.1 10.0 0.3 8.0 0.2 1.0 0.2 0.15+0.10 -0.05 0.5 0.2 0.10 0.10 INCHES 0.639 MAX. 0.025 MAX. 0.026 (T.P.) 0.012+0.004 -0.005 0.005 0.003 0.079 MAX. 0.067 0.004 0.394 +0.012 -0.013 0.315 0.008 0.039+0.009 -0.008 0.006+0.004 -0.002 0.020+0.008 -0.009 0.004 0.004 25 PD9611 7. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, please contact your NEC sales representative. SURFACE MOUNT TYPE PD9611GT: 48-pin shrink SOP (375 mil) Recommended Condition Symbol IR-35-103-2 Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235 C Duration: 30 sec. max. (210 C or above) Number of times: 2 max. Time limit: 3 days Note (thereafter, 10-hour prebaking at 125 C required.) Pin heating -- Note For the storage period after unpacking from the dry-pack, storage conditions are max. 25 C, 65 % RH. 26 PD9611 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 27 PD9611 [MEMO] The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 |
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